Effect Of The Code On Timer On STM32 Board In C Assignment Solution

Instructions

Objective

Write a C program to find the effect of the code on timer on STM32 boards

Requirements and Specifications

Consider the following FIVE lines in the SystemInit() function

RCC->CR = (uint32_t)0x00000001;

RCC->CFGR = 0x00000000;

RCC->CR &= (uint32_tOxFEF6FFFF;

RCC->PLLCFGR = 0x24003010;

RCC->CR &= (uint32_t)0xFFFBFFFF;

These five lines are configuring the clock. For each line, briefly explain what is happening by referring to Chapter 7 in the STM32F407 Reference Manual (RM0090).

What is the SYSTEM CLOCK SYSCLK when these 5 lines are executed?

Solution

RCR->CR |= (uint32_t) 0x00000001;

This line sets the bit HSION (internal high-speed clock enable) from the RCC clock control register (CR) to 1. By setting it to 1 we turn on the 16MHz internal high-speed clock.

RCC->CFGR = 0x00000000;

This line clears all the bits in the clock configuration register (CFGR) to zero. Thus, sets the register to it reset value of 0. Whith this, the following configuration is selected:

System clock = HSI oscillator

AHB prescaler = system clock not divided

APB low speed prescaler = AHB clock not divided

APB high speed prescaler = AHB clock not divided

HSE division factor for RTC clock = no clock

Microcontroller clock output 1 = HSI clock selected

I2S clock selection = PLLI2S clock used as I2S clock source

MCO1 prescaler = no division

MCO2 prescaler = no division

Microcontroller clock output 2 = system clock (SYSCLK) selected

We can thus see that the system clock is set to use the internal high speed clock and AHB and APB clocks are set to the same clock (16MHz) without scaling.

RCR->CR &= (uint32_t) 0xFEF6FFFF;

This line clears bits 24, 19 and 16 of the RCC clock control register (CR) to zero.

Bit 24 is PLLON, main PLL enable, by clearing it we are turning off the main PLL.

Bit 19 is CSSON, clock security system enable, by clearing it we are turning the clock security system off thus disabling the failure detection of the HSE clock.

Bit 16 is HSEON, HSE clock enable, by clearing it we are turning the high-speed external oscillator OFF.

We can thus see that we are disabling the main PLL, the HSE security system and the high speed external clock itself.

RCC->PLLCFGR = 0x24003010;

This line selects the configuration of the PLL configuration register (PLLCFGR). The given value corresponds to the reset value of the PPLCFGR. With this, the following configuration is selected:

Division factor of the main PLL for the USB OTG FS SDIO and random number gen. clocks (PLLQ) = 4

Main PLL and audio PLL entry clock source (PLLSRC) = HSI clock

Division factor of the main PLL for the main system clock (PLLP) = 2

Multiplication factor of the main PLL for VCO (PLLN) = 192

Division factor of the main PLL and audio PLL (PLLM) = 16

Thus the clock for the main PLL is set to (HSI/16)*192/2 = 96MHz for the main system clock output and to (HSI/16)*192/4 = 48MHz for the USB OTG FS SDIO and rand. num. gen. clocks.

RCR->CR &= (uint32_t) 0xFFFBFFFF;

This line clears bit 18 of the RCC clock control register (CR) to zero.

Bit 18 is HSEBYP, high-speed external clock bypass, by clearing this bit we are not bypassing the HSE oscillator and thus an external clock will not be provided.

What is the SYSTEM CLOCK SYSCLK when these 5 lines are executed?

= 16MHz